Project 10: PWM Generator (LED Dimmer / Servo Control)

Generate PWM with programmable duty cycle for LED dimming or servo control.

Quick Reference

Attribute Value
Difficulty Intermediate
Time Estimate 4-6 hours
Main Programming Language Verilog (Alternatives: VHDL, SystemVerilog)
Alternative Programming Languages VHDL, SystemVerilog
Coolness Level High
Business Potential Medium
Prerequisites Counters, Comparators
Key Topics PWM, Duty cycle, Resolution

1. Learning Objectives

  1. Generate PWM from a counter
  2. Control duty cycle at runtime
  3. Choose frequency vs resolution

2. All Theory Needed (Per-Concept Breakdown)

Counters and Clock Enables

Description/Expanded Explanation of the concept

Counters are registers that increment or decrement each clock cycle. Clock enables allow you to update a register only when needed, which is safer than gating clocks. They are essential for timing, PWM, and pacing visible outputs.

Definitions & Key Terms
  • Counter -> register that increments/decrements
  • Clock enable -> condition that allows a register update
  • Prescaler -> counter used to slow down a signal
Mental Model Diagram (ASCII)
clk -> [counter] --tick--> [slow logic]

Clock divider tick pipeline

How It Works (Step-by-Step)
  1. Increment counter each clock edge.
  2. When counter reaches a limit, assert a tick.
  3. Use tick as a clock enable for slower logic.
Minimal Concrete Example
if (tick) out <= out + 1;
Common Misconceptions
  • “Gating the clock is simpler.” -> It can break timing and glitch.
  • “Counters are always free.” -> Wide counters consume resources.
Check-Your-Understanding Questions
  1. Why use clock enables instead of gating clocks?
  2. How do you choose counter width for a target frequency?
  3. What happens when a counter overflows?
Where You’ll Apply It
  • This project: used in Section 3.2 and Section 5
  • Also used in: P08-shift-register-led-chaser.md, P10-pwm-generator-led-dimmer-servo-control.md

Verification with Testbenches and Waveforms

Description/Expanded Explanation of the concept

Testbenches are simulation-only modules that apply stimulus and check outputs. Waveforms (VCD) are the hardware engineer’s microscope; they reveal timing, glitches, and ordering problems. A good testbench is deterministic and covers edge cases.

Definitions & Key Terms
  • Testbench -> a non-synthesizable module that drives a DUT
  • VCD -> Value Change Dump waveform file
  • Deterministic test -> same inputs produce same outputs every run
Mental Model Diagram (ASCII)
[Testbench] -> [DUT] -> [VCD] -> [GTKWave]

Testbench DUT VCD GTKWave flow

How It Works (Step-by-Step)
  1. Initialize inputs to known values.
  2. Apply stimulus over time.
  3. Dump waveforms and check outputs.
  4. Add assertions or PASS/FAIL messages.
Minimal Concrete Example
initial begin
  $dumpfile("wave.vcd");
  $dumpvars(0, tb);
  a = 0; b = 1; #10;
  $finish;
end
Common Misconceptions
  • “If it simulates once, it’s correct.” -> Cover all relevant cases.
  • “Waveforms are optional.” -> They are often the only way to debug timing.
Check-Your-Understanding Questions
  1. Why keep testbench and DUT separate?
  2. What is the purpose of $dumpvars?
  3. How do you make a testbench deterministic?
Where You’ll Apply It
  • This project: used throughout Section 6 (testing)
  • Also used in: all other projects in this folder

3. Project Specification

3.1 What You Will Build

A PWM block with configurable duty and optional prescaler.

3.2 Functional Requirements

  1. Requirement 1: Output high when counter < duty
  2. Requirement 2: Allow duty updates without glitches
  3. Requirement 3: Support a stable PWM frequency

3.3 Non-Functional Requirements

  • Performance: Stable operation at the target clock and interfaces.
  • Reliability: Deterministic outputs on all defined inputs.
  • Usability: Clear ports and documented behavior.

3.4 Example Usage / Output

{p['example_usage']}

3.5 Data Formats / Schemas / Protocols

{p[‘data_format’]}

3.6 Edge Cases

  • Duty=0
  • Duty=max

3.7 Real World Outcome

3.7.1 How to Run (Copy/Paste)

vvp pwm_tb

3.7.2 Golden Path Demo (Deterministic)

Run the demo command above with the provided testbench and confirm the outputs match the golden transcript.

3.7.3 CLI Transcript

Duty=10% -> narrow pulse
Duty=90% -> wide pulse

3.7.4 Failure Demo (Expected)

# Example failure case
ERROR: Output mismatch at vector 3
Expected: 0x0A, Got: 0x0B
EXIT CODE: 1

Notes:

  • Exit code 0 indicates all tests passed
  • Exit code 1 indicates a test failure

4. Solution Architecture

4.1 High-Level Design

[inputs] -> [core logic] -> [outputs]

Core logic flow

4.2 Key Components

Component Responsibility
counter Free-running counter
compare Duty comparator

4.3 Data Structures (No Full Code)

// Example signals (adapt to your design)
reg [7:0] state_reg;
reg [7:0] data_reg;

4.4 Algorithm Overview

Key Algorithm: Core control flow

  1. Initialize state/reset conditions.
  2. Apply inputs and compute outputs.
  3. Update state on clock edges (if sequential).

Complexity Analysis:

  • Time: O(1) per cycle
  • Space: O(N) for registers and logic

5. Implementation Guide

5.1 Development Environment Setup

iverilog -v
# Ensure GTKWave is installed for waveform viewing

5.2 Project Structure

project-root/
|-- src/
|   |-- top.v
|   |-- core.v
|-- tb/
|   |-- tb.v
|-- Makefile
|-- README.md

Project folder structure

5.3 The Core Question You’re Answering

“How can a digital signal emulate analog behavior?”

5.4 Concepts You Must Understand First

  • Counters
  • Comparators

5.5 Questions to Guide Your Design

  • What PWM frequency is required?
  • What resolution is acceptable?

5.6 Thinking Exercise

Compute PWM frequency for a 50 MHz clock and 8-bit counter.

5.7 The Interview Questions They’ll Ask

  • What is duty cycle?
  • How do you trade frequency vs resolution?

5.8 Hints in Layers

  • Use a counter and compare to duty.
  • Update duty on counter wrap to avoid glitches.

5.9 Books That Will Help

Topic Book Chapter
Embedded timing Making Embedded Systems Ch. 8

5.10 Implementation Phases

Phase 1: Foundation

Goals:

  • Establish core module structure
  • Implement minimal behavior

Tasks:

  1. Scaffold module ports and internal signals
  2. Write a minimal testbench that compiles

Checkpoint: Simulation runs without errors

Phase 2: Core Functionality

Goals:

  • Implement full logic
  • Verify edge cases

Tasks:

  1. Complete core logic
  2. Add directed tests for edge cases

Checkpoint: All tests pass and waveforms match expectations

Phase 3: Polish & Edge Cases

Goals:

  • Improve readability
  • Document behavior

Tasks:

  1. Add comments and README notes
  2. Expand tests for unusual inputs

Checkpoint: Design is deterministic and documented

5.11 Key Implementation Decisions

Decision Options Recommendation Rationale
Reset strategy Sync / Async Sync Simpler timing closure
Test coverage Directed / Exhaustive Exhaustive for small logic Prevents missed cases

6. Testing Strategy

6.1 Test Categories

Category Purpose Examples
Unit Tests Test core logic Small vectors
Integration Tests Test modules together Full system
Edge Case Tests Boundary conditions Max/min values

6.2 Critical Test Cases

  1. Test 1: Duty 0% and 100% cases
  2. Test 2: Verify frequency with period measurement

6.3 Test Data

Use deterministic vectors and document expected outputs.

7. Common Pitfalls & Debugging

7.1 Frequent Mistakes

Pitfall Symptom Solution
Visible flicker PWM too slow Increase frequency

7.2 Debugging Strategies

  • Inspect waveforms at key internal signals
  • Add temporary debug outputs to verify state
  • Reduce testcases to the smallest failing case

7.3 Performance Traps

  • Overly wide counters or combinational paths can reduce max clock

8. Extensions & Challenges

8.1 Beginner Extensions

  • Add parameterization for widths
  • Add optional features (enable, reset)

8.2 Intermediate Extensions

  • Add configuration registers
  • Build a simple driver or demo program

8.3 Advanced Extensions

  • Integrate with another project in this series
  • Implement a hardware demo on FPGA

9. Real-World Connections

9.1 Industry Applications

  • Digital control systems and embedded peripherals
  • FPGA prototyping and validation
  • Yosys / nextpnr toolchain for open-source FPGA flow
  • Example HDL projects in the FPGA community

9.3 Interview Relevance

  • Demonstrates RTL thinking and verification skills

10. Resources

10.1 Essential Reading

  • Making Embedded Systems - Focus on Ch. 8

10.2 Video Resources

  • Search for project-specific HDL walkthroughs and waveforms

10.3 Tools & Documentation

  • Icarus Verilog
  • GTKWave
  • See adjacent projects in VERILOG_FROM_ZERO_PROJECTS/

11. Self-Assessment Checklist

11.1 Understanding

  • I can explain the core concept without notes
  • I can predict waveform behavior for basic inputs

11.2 Implementation

  • All functional requirements are met
  • All tests pass
  • Edge cases are documented

11.3 Growth

  • I can explain this project in an interview
  • I documented at least one lesson learned

12. Submission / Completion Criteria

Minimum Viable Completion:

  • Functional requirements implemented
  • Testbench passes
  • Waveforms inspected

Full Completion:

  • All minimum criteria plus
  • Edge cases covered and documented

Excellence (Going Above & Beyond):

  • Hardware demo on FPGA
  • Clear write-up of lessons learned

    Appendix A: Deep Dive Walkthrough

A.1 Signal Map and Invariants

  • Inputs: clk, reset, duty[7:0], period[15:0] (or fixed)
  • Output: pwm_out

Invariant: pwm_out is high for duty counts out of each period.

A.2 PWM Core Equation

pwm_out = (counter < duty) ? 1 : 0

A.3 Example for LED Dimming

  • period = 255, duty = 64 -> 25% brightness.

A.4 Servo Control Mapping (50 Hz)

  • Period = 20 ms.
  • High pulse 1.0 ms -> ~0 degrees.
  • High pulse 1.5 ms -> ~90 degrees.
  • High pulse 2.0 ms -> ~180 degrees.

A.5 Deterministic Test Sequence

  • Set duty to 0 -> output always low.
  • Set duty to max -> output always high.
  • Set duty to half -> output high half the period.

A.6 Waveform Debug Tip

If PWM frequency is wrong, check the counter reset point and clock divider.

13. Deep Dive Appendix

13.1 Timing and Resource Budget

  • PWM frequency = clk / period_count. Resolution is log2(period_count) bits.
  • For LEDs, keep PWM > 200 Hz to avoid flicker.
  • For servos, use 50 Hz with 1-2 ms pulse width (duty about 5-10%).

13.2 Waveform Interpretation Guide

  • pwm_out should be high for duty counts and low for the rest.
  • Duty changes should take effect cleanly at cycle boundaries.

Example:

period=1000, duty=250 -> 25% duty
period=1000, duty=750 -> 75% duty

13.3 Hardware Bring-Up Notes

  • Use a resistor and LED for a dimming demo.
  • For servos, ensure the output is 3.3V tolerant or use a level shifter.
  • If the servo jitters, check your period accuracy and grounding.

13.4 Alternate Implementations and Trade-offs

  • Center-aligned PWM reduces spectral noise but is more complex.
  • Dithered PWM improves effective resolution by toggling between two duty values.
  • Multi-channel PWM shares the same counter with multiple compare values.

13.5 Additional Exercises

  • Add a gamma-corrected brightness curve for LEDs.
  • Build two-channel PWM with independent duty settings.
  • Implement a servo sweep state machine with configurable endpoints.