VERILOG FROM ZERO PROJECTS

Verilog from Absolute Zero: Project-Based Learning Path

What is Verilog?

Verilog is NOT programming – it’s hardware description. This is the most important mental shift you need to make.

Traditional Programming	Verilog (Hardware Description)
Instructions execute one after another	Everything happens simultaneously
Variables hold values	Wires carry signals, registers store state
Functions are called	Modules are instantiated (like placing a chip on a board)
Loops iterate over time	Loops generate hardware (unroll at compile time)
if/else chooses a path	if/else creates MUXes (both paths exist!)

The Mental Model

Think of Verilog like drawing a circuit diagram with code. When you write:

assign out = a & b;

You’re not saying “compute a AND b and store it in out.” You’re saying “there exists a wire called out that is permanently connected to the output of an AND gate whose inputs are a and b.”

Everything you write exists simultaneously as physical hardware.

Tools You Need (All Free)

For Simulation (Start Here!)

Icarus Verilog - Free, open-source Verilog simulator
GTKWave - Waveform viewer to see your signals

Installation:

# macOS
brew install icarus-verilog gtkwave

# Ubuntu/Debian
sudo apt-get install iverilog gtkwave

# Windows: Download from http://bleyer.org/icarus/

For Real Hardware (Later)

TinyFPGA BX (~$38) - iCE40 FPGA, USB programmable
iCEBreaker (~$70) - More I/O, great for beginners
IceStorm Toolchain - Open source synthesis tools

Core Concept Analysis

To truly understand Verilog, you need to master these fundamental concepts:

Concept	What It Means	Project That Teaches It
Modules	The basic building block (like a function that becomes a chip)	Gate Library
Wires	Connections that carry values (combinational)	All projects
Registers (reg)	Storage elements that hold state	Counter, Shift Register
*always @()**	Combinational logic block	Decoder, ALU
always @(posedge clk)	Sequential logic (clocked)	Counter, FSM
Assign	Continuous assignment (wires)	Gates, Adders
Blocking (=) vs Non-blocking (<=)	Execution semantics	Counter, FSM
Testbenches	How to simulate and verify	Every project
State Machines	Sequential behavior	Traffic Light, UART
Parameters	Configurable/reusable modules	Parameterized Counter

Project Progression Overview

Level 1: COMBINATIONAL LOGIC (no clock, pure logic gates)
├── Project 1: Gate Library (AND, OR, NOT, XOR)
├── Project 2: 4-to-1 Multiplexer
├── Project 3: 7-Segment Decoder
├── Project 4: 4-bit Ripple Carry Adder
└── Project 5: 8-bit ALU

Level 2: SEQUENTIAL LOGIC (registers, counters, clocks)
├── Project 6: D Flip-Flop
├── Project 7: 4-bit Counter
├── Project 8: Shift Register (LED Chaser)
├── Project 9: Debouncer (Real Hardware Skill)
└── Project 10: PWM Generator

Level 3: STATE MACHINES (complex sequential behavior)
├── Project 11: Traffic Light Controller
├── Project 12: Vending Machine
└── Project 13: Pattern Detector

Level 4: MEMORY & INTERFACES (real-world protocols)
├── Project 14: Simple RAM (8x8)
├── Project 15: UART Transmitter
├── Project 16: UART Receiver
└── Project 17: SPI Master

Level 5: COMPLEX SYSTEMS (putting it all together)
├── Project 18: VGA Pattern Generator
├── Project 19: Simple Calculator with Display
└── Project 20: Pong Game on VGA

FINAL PROJECT: Simple 8-bit CPU

Level 1: Combinational Logic Projects

These projects have NO clock. The outputs are purely determined by the inputs, like logic gates on a breadboard.

Project 1: Digital Gate Library

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog, Chisel (Scala-based)
Coolness Level: Level 1: Pure Corporate Snoozefest
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 1: Beginner (The Tinkerer)
Knowledge Area: Digital Logic / HDL Fundamentals
Software or Tool: Icarus Verilog, GTKWave
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A library of basic logic gates (AND, OR, NOT, XOR, NAND, NOR) with a testbench that proves each gate works correctly.

Why it teaches Verilog fundamentals: This is your “Hello World.” You’ll learn module structure, ports (inputs/outputs), assign statements, and how to write your first testbench. You’ll see waveforms for the first time.

Core challenges you’ll face:

Understanding module syntax (inputs, outputs, body) → maps to Verilog structure
Using assign for continuous logic → maps to combinational logic
Writing your first testbench with $dumpfile/$dumpvars → maps to simulation workflow
Reading waveforms in GTKWave → maps to debugging hardware

Key Concepts:

Module Structure: “Digital Design and Computer Architecture” Chapter 4.1 - Harris & Harris
Assign Statements: ChipVerify Verilog Tutorial - Assign section
Testbench Basics: ASIC World Verilog Tutorial - Testbench section

Difficulty: Beginner Time estimate: 2-3 hours Prerequisites: None (this is your starting point)

Real world outcome:

$ iverilog -o gates_tb gates.v gates_tb.v
$ vvp gates_tb
Testing AND gate...
  a=0, b=0 -> out=0 ✓
  a=0, b=1 -> out=0 ✓
  a=1, b=0 -> out=0 ✓
  a=1, b=1 -> out=1 ✓
All tests passed!
$ gtkwave gates.vcd
# See beautiful waveforms showing all gate operations!

Learning milestones:

First module compiles without errors → You understand Verilog syntax
Testbench runs and produces VCD file → You understand the simulation workflow
Waveforms display in GTKWave → You can debug hardware visually

Project 2: 4-to-1 Multiplexer

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog, Amaranth (Python-based)
Coolness Level: Level 2: Practical but Forgettable
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 1: Beginner (The Tinkerer)
Knowledge Area: Combinational Logic / Data Selection
Software or Tool: Icarus Verilog, GTKWave
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A multiplexer that selects one of four inputs based on a 2-bit select signal. Then expand to an 8-to-1 MUX.

Why it teaches Verilog: Multiplexers are the foundation of all data routing in digital circuits. You’ll learn case statements, conditional operators (? :), and how if/else in Verilog creates hardware, not sequential execution.

Core challenges you’ll face:

Understanding that if/else creates a MUX (both paths EXIST as hardware) → maps to hardware vs software thinking
Using always @(*) for combinational logic → maps to sensitivity lists
Comparing different implementation styles (assign vs always) → maps to coding styles

Key Concepts:

Multiplexer Design: “Digital Design and Computer Architecture” Chapter 2.8 - Harris & Harris
always @(*) blocks: Nandland - Verilog Always Block
Case Statements: “Digital Design and Computer Architecture” Chapter 4.2 - Harris & Harris

Difficulty: Beginner Time estimate: 2-3 hours Prerequisites: Project 1 (Gate Library)

Real world outcome:

$ vvp mux_tb
Testing 4-to-1 MUX...
  sel=00: selected input[0]=1010 → out=1010 ✓
  sel=01: selected input[1]=0101 → out=0101 ✓
  sel=10: selected input[2]=1100 → out=1100 ✓
  sel=11: selected input[3]=0011 → out=0011 ✓

Learning milestones:

MUX works with assign and ternary operator → You understand continuous assignment
MUX works with always @(*) case → You understand behavioral combinational logic
8-to-1 MUX works → You can scale designs

Project 3: 7-Segment Display Decoder

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog, SpinalHDL
Coolness Level: Level 3: Genuinely Clever
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 1: Beginner (The Tinkerer)
Knowledge Area: Combinational Logic / Display Interfaces
Software or Tool: Icarus Verilog, TinyFPGA BX (for hardware)
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A decoder that takes a 4-bit binary number (0-15) and outputs the 7 signals needed to display that digit on a 7-segment LED display.

Why it teaches Verilog: This is a pure combinational lookup table. You’ll deeply understand case statements and see how they synthesize to actual hardware. Plus, it’s satisfying to see real LEDs light up!

Core challenges you’ll face:

Mapping binary values to 7-segment patterns → maps to truth table implementation
Handling hexadecimal digits (A-F) → maps to complete case coverage
Active-low vs active-high LED logic → maps to real hardware considerations

Key Concepts:

Decoders: “Digital Design and Computer Architecture” Chapter 2.9 - Harris & Harris
Case Statement Completeness: ASIC World - Case Statement
Seven Segment Displays: Nandland - 7-Segment Tutorial

Difficulty: Beginner Time estimate: 3-4 hours Prerequisites: Project 2 (Multiplexer)

Real world outcome:

Simulation output:
  input=0000 (0)  → segments=0111111 (displays "0")
  input=0001 (1)  → segments=0000110 (displays "1")
  input=1001 (9)  → segments=1101111 (displays "9")
  input=1010 (10) → segments=1110111 (displays "A")

On real FPGA: Connect 7 LEDs and see actual digits light up!

Learning milestones:

All digits 0-9 display correctly → You understand case statements
Hex digits A-F work → You’ve handled all cases
Running on real FPGA with physical LEDs → First taste of real hardware!

Project 4: 4-bit Ripple Carry Adder

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog, Clash (Haskell-based)
Coolness Level: Level 3: Genuinely Clever
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 2: Intermediate (The Developer)
Knowledge Area: Arithmetic Circuits / Computer Architecture
Software or Tool: Icarus Verilog, GTKWave
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A 4-bit adder constructed from full adders, where the carry “ripples” from one bit to the next. Then compare it to Verilog’s built-in + operator.

Why it teaches Verilog: This project introduces module instantiation – creating instances of smaller modules inside larger ones. This is how real hardware is hierarchically designed.

Core challenges you’ll face:

Building a full adder from half adders → maps to hierarchical design
Instantiating modules and connecting wires → maps to structural Verilog
Understanding propagation delay (why ripple carry is slow) → maps to timing concepts

Key Concepts:

Full Adder Design: “Digital Design and Computer Architecture” Chapter 5.2 - Harris & Harris
Module Instantiation: ChipVerify - Module Instantiation
Carry Propagation: “Computer Systems: A Programmer’s Perspective” Chapter 2 - Bryant & O’Hallaron

Difficulty: Beginner-Intermediate Time estimate: 4-5 hours Prerequisites: Project 1 (Gate Library)

Real world outcome:

$ vvp adder_tb
Testing 4-bit Ripple Carry Adder...
  0101 + 0011 = 1000 (5 + 3 = 8) ✓
  1111 + 0001 = 0000 with carry=1 (15 + 1 = 16, overflow!) ✓
  1010 + 0101 = 1111 (10 + 5 = 15) ✓

GTKWave shows carry rippling through each stage with visible delays!

Learning milestones:

Full adder module works → You understand single-bit arithmetic
4-bit adder chains full adders correctly → You understand module instantiation
You see the “ripple” in waveforms → You understand propagation delay

Project 5: 8-bit ALU (Arithmetic Logic Unit)

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog, nMigen
Coolness Level: Level 4: Hardcore Tech Flex
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 2: Intermediate (The Developer)
Knowledge Area: Computer Architecture / CPU Design
Software or Tool: Icarus Verilog, GTKWave
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: An 8-bit ALU that performs ADD, SUB, AND, OR, XOR, NOT, shift left, shift right, and comparison operations based on a 4-bit opcode.

Why it teaches Verilog: The ALU is the heart of every CPU. This project combines everything: MUXes select operations, adders perform arithmetic, and logic gates handle bitwise ops. You’re building the core of a computer!

Core challenges you’ll face:

Selecting between multiple operations with a MUX → maps to control logic
Implementing subtraction with two’s complement → maps to arithmetic fundamentals
Generating status flags (zero, carry, negative) → maps to CPU status registers
Parameterizing bit width → maps to reusable design

Key Concepts:

ALU Design: “Digital Design and Computer Architecture” Chapter 5.3 - Harris & Harris
Two’s Complement: “Computer Systems: A Programmer’s Perspective” Chapter 2.3 - Bryant & O’Hallaron
Status Flags: “Code: The Hidden Language” Chapter 18 - Charles Petzold

Difficulty: Intermediate Time estimate: 1 week Prerequisites: Project 4 (Adder)

Real world outcome:

$ vvp alu_tb
Testing 8-bit ALU...
  OP=ADD: 0x45 + 0x23 = 0x68, Z=0, C=0, N=0 ✓
  OP=SUB: 0x45 - 0x23 = 0x22, Z=0, C=0, N=0 ✓
  OP=SUB: 0x23 - 0x45 = 0xDE, Z=0, C=1, N=1 ✓ (borrow/negative)
  OP=AND: 0xFF & 0x0F = 0x0F ✓
  OP=SHL: 0x01 << 3 = 0x08 ✓
  OP=CMP: 0x45 == 0x45? Z=1 ✓

This is the core of a CPU - you built it!

Learning milestones:

ADD/SUB work with carry/borrow → You understand binary arithmetic in hardware
All logic operations work → You’ve built a complete ALU
Status flags are correct → You understand CPU control flow

Level 2: Sequential Logic Projects

These projects use a clock. State is stored in registers and changes on clock edges.

Project 6: D Flip-Flop (The Building Block of Memory)

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 2: Practical but Forgettable
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 1: Beginner (The Tinkerer)
Knowledge Area: Sequential Logic / Storage Elements
Software or Tool: Icarus Verilog, GTKWave
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A D flip-flop with synchronous reset and enable. Then a register made of multiple flip-flops.

Why it teaches Verilog: This is your introduction to always @(posedge clk) – the fundamental pattern for all sequential logic. You’ll understand the difference between = (blocking) and <= (non-blocking) assignments.

Core challenges you’ll face:

Understanding clock edges (posedge/negedge) → maps to synchronous logic
Using non-blocking assignments (<=) → maps to parallel hardware behavior
Adding reset and enable signals → maps to control inputs

Key Concepts:

Flip-Flops: “Digital Design and Computer Architecture” Chapter 3.2 - Harris & Harris
Blocking vs Non-blocking: StackOverflow - Blocking vs Non-blocking
Clock Edge Detection: “Operating Systems: Three Easy Pieces” - Concurrency chapter (for timing intuition)

Difficulty: Beginner Time estimate: 2-3 hours Prerequisites: Projects 1-2

Real world outcome:

GTKWave shows:
  - D changes randomly
  - Q only updates on rising clock edge
  - When reset=1, Q goes to 0 regardless of D
  - When enable=0, Q holds its value

You can SEE time in the waveform - this is sequential logic!

Learning milestones:

Q follows D on clock edge → You understand edge-triggered behavior
Reset works synchronously → You understand control signals
8-bit register works → You can build storage elements

Project 7: 4-bit Up/Down Counter with Load

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog, Chisel
Coolness Level: Level 3: Genuinely Clever
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 2: Intermediate (The Developer)
Knowledge Area: Sequential Logic / Counters
Software or Tool: Icarus Verilog, TinyFPGA BX
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A counter that can count up, count down, load a specific value, and reset. Add a terminal count output for chaining counters.

Why it teaches Verilog: Counters are everywhere in digital design – timers, addresses, state machines. You’ll practice sequential logic and learn about overflow/underflow handling.

Core challenges you’ll face:

Incrementing/decrementing with overflow handling → maps to arithmetic in hardware
Parallel load functionality → maps to register control
Terminal count for cascading → maps to hierarchical counters

Key Concepts:

Counter Design: “Digital Design and Computer Architecture” Chapter 3.4 - Harris & Harris
Overflow Detection: “Computer Systems: A Programmer’s Perspective” Chapter 2.3 - Bryant & O’Hallaron
Parameterized Counters: ChipVerify - Parameters

Difficulty: Intermediate Time estimate: 4-5 hours Prerequisites: Project 6 (Flip-Flop)

Real world outcome:

On FPGA with 4 LEDs:
  - Watch binary count: 0000 → 0001 → 0010 → ... → 1111 → 0000
  - Press button: count direction reverses!
  - Hold load button: counter jumps to switch value

You built a real piece of digital hardware!

Learning milestones:

Counter counts up correctly → You understand sequential increment
Up/down control works → You understand conditional sequential logic
Running on FPGA with visible LEDs → You’ve made real hardware!

Project 8: Shift Register LED Chaser

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 3: Genuinely Clever
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 2: Intermediate (The Developer)
Knowledge Area: Sequential Logic / Shift Registers
Software or Tool: Icarus Verilog, TinyFPGA BX or iCEBreaker
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: An 8-bit shift register that creates a “Knight Rider” LED chaser effect – a lit LED bounces back and forth across 8 LEDs.

Why it teaches Verilog: Shift registers are fundamental building blocks for serial communication (UART, SPI), CRC calculation, and more. Plus, blinking LEDs in cool patterns is incredibly satisfying!

Core challenges you’ll face:

Shifting bits left/right → maps to shift register operation
Creating a clock divider (FPGA clock is too fast for eyes) → maps to timing generation
Detecting edges for direction change → maps to boundary conditions

Key Concepts:

Shift Registers: “Digital Design and Computer Architecture” Chapter 3.3 - Harris & Harris
Clock Dividers: FPGA Tutorial - Clock Divider
LFSR (bonus): Wikipedia - Linear Feedback Shift Register

Difficulty: Intermediate Time estimate: 1 weekend Prerequisites: Project 7 (Counter)

Real world outcome:

On FPGA with 8 LEDs:
  ●○○○○○○○ → ○●○○○○○○ → ○○●○○○○○ → ... → ○○○○○○○● → ○○○○○○●○ → ...

The classic "Knight Rider" / "Cylon" effect!

Learning milestones:

Basic shift works → You understand bit shifting in hardware
Clock divider makes it visible → You understand timing generation
Bounce effect works → You’ve built a complete system

Project 9: Button Debouncer

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 3: Genuinely Clever
Business Potential: 2. The “Micro-SaaS / Pro Tool” (Solo-Preneur Potential)
Difficulty: Level 2: Intermediate (The Developer)
Knowledge Area: Digital Interfaces / Real Hardware
Software or Tool: TinyFPGA BX, iCEBreaker, any FPGA with buttons
Main Book: “Making Embedded Systems” by Elecia White

What you’ll build: A debouncing circuit that turns noisy mechanical button presses into clean single pulses.

Why it teaches Verilog: This is your first encounter with real-world hardware imperfection. Mechanical buttons “bounce” – a single press creates multiple electrical transitions. Every real FPGA project needs this!

Core challenges you’ll face:

Understanding button bounce (why raw buttons are unreliable) → maps to real-world signals
Implementing a timer to filter noise → maps to timing-based filtering
Generating a single-cycle pulse from a long press → maps to edge detection

Key Concepts:

Switch Debouncing: “Making Embedded Systems” Chapter 8 - Elecia White
Metastability: “Digital Design and Computer Architecture” Chapter 3.5 - Harris & Harris
Synchronizers: FPGA Tutorial - Metastability

Difficulty: Intermediate Time estimate: 4-5 hours Prerequisites: Project 7 (Counter)

Real world outcome:

Without debouncer:
  Press button once → Counter shows: 1... 4... 7... 12... (random bounces!)

With debouncer:
  Press button once → Counter shows: 1 (clean, reliable!)

You've solved a real embedded systems problem!

Learning milestones:

You see bounce on oscilloscope/LEDs → You understand the problem
Debouncer produces clean signals → You’ve solved it
Edge detector gives single pulse → You can use buttons reliably

Project 10: PWM Generator (LED Dimmer / Servo Control)

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 3: Genuinely Clever
Business Potential: 2. The “Micro-SaaS / Pro Tool” (Solo-Preneur Potential)
Difficulty: Level 2: Intermediate (The Developer)
Knowledge Area: Digital-to-Analog / Motor Control
Software or Tool: TinyFPGA BX with LED or servo
Main Book: “Making Embedded Systems” by Elecia White

What you’ll build: A Pulse Width Modulation generator that can dim an LED or control a servo motor position.

Why it teaches Verilog: PWM is the bridge between digital and analog worlds. By varying the duty cycle, you can control brightness, motor speed, or servo position. This is real embedded systems work!

Core challenges you’ll face:

Generating a variable duty cycle → maps to comparison and timing
Creating configurable frequency → maps to parameterization
Smooth fading effect (bonus) → maps to state machines for animations

Key Concepts:

PWM Basics: “Making Embedded Systems” Chapter 6 - Elecia White
Servo Control Timing: Typical servo needs 1-2ms pulses at 50Hz
Counter-Based PWM: Nandland - PWM Tutorial

Difficulty: Intermediate Time estimate: 4-5 hours Prerequisites: Project 7 (Counter)

Real world outcome:

With LED:
  - Duty cycle = 10% → LED barely glowing
  - Duty cycle = 50% → LED medium brightness
  - Duty cycle = 100% → LED full brightness

With Servo:
  - 1.0ms pulse → Servo at 0°
  - 1.5ms pulse → Servo at 90°
  - 2.0ms pulse → Servo at 180°

You're controlling real physical things with Verilog!

Learning milestones:

PWM waveform visible in GTKWave → You understand the concept
LED brightness changes → You’ve bridged digital to analog
Servo responds to position changes → You’re controlling motors!

Level 3: State Machine Projects

State machines are the heart of complex digital behavior. They’re how you implement protocols, controllers, and any system with memory of what happened before.

Project 11: Traffic Light Controller

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog, Chisel
Coolness Level: Level 3: Genuinely Clever
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 2: Intermediate (The Developer)
Knowledge Area: Finite State Machines / Control Systems
Software or Tool: Icarus Verilog, TinyFPGA BX with 6 LEDs
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A traffic light controller for a 4-way intersection with proper timing and sequencing: Green → Yellow → Red, with safe overlap periods.

Why it teaches Verilog: This is your first real Finite State Machine (FSM). You’ll learn state encoding, state transitions, output logic, and timing. FSMs are how you implement any complex behavior!

Core challenges you’ll face:

Defining states (GREEN_NS, YELLOW_NS, RED_ALL, etc.) → maps to state encoding
Implementing timing for each state → maps to timer-based transitions
Ensuring safety (no conflicting greens) → maps to correctness verification
Moore vs Mealy machines → maps to FSM architecture

Key Concepts:

FSM Design: “Digital Design and Computer Architecture” Chapter 3.4 - Harris & Harris
State Encoding: “Language Implementation Patterns” Chapter 2 - Terence Parr
Timing Diagrams: ASIC World - FSM Tutorial

Difficulty: Intermediate Time estimate: 1 weekend Prerequisites: Project 7 (Counter), Project 9 (Debouncer)

Real world outcome:

On FPGA with 6 LEDs (2 sets of R/Y/G):

  NS=🟢 EW=🔴 (10 sec) → NS=🟡 EW=🔴 (3 sec) → NS=🔴 EW=🔴 (1 sec) →
  NS=🔴 EW=🟢 (10 sec) → NS=🔴 EW=🟡 (3 sec) → NS=🔴 EW=🔴 (1 sec) → repeat

Optional: Add pedestrian crossing button!

Learning milestones:

States transition correctly → You understand FSM basics
Timing is accurate → You’ve integrated counters with FSMs
No unsafe states ever occur → You’ve verified correctness

Project 12: Vending Machine Controller

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 3: Genuinely Clever
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 3: Advanced (The Engineer)
Knowledge Area: Finite State Machines / Control Systems
Software or Tool: Icarus Verilog, GTKWave
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A vending machine that accepts coins (5¢, 10¢, 25¢), tracks total, dispenses when enough money is inserted, and returns change.

Why it teaches Verilog: This FSM has more complex transitions based on multiple inputs. You’ll handle arithmetic within a state machine and learn about output timing.

Core challenges you’ll face:

Managing accumulator state (total money) → maps to stateful computation
Multiple input handling (different coin types) → maps to complex transitions
Change calculation → maps to arithmetic in FSMs
Timeout (return coins if abandoned) → maps to watchdog timers

Key Concepts:

Complex FSMs: “Digital Design and Computer Architecture” Chapter 3.4.4 - Harris & Harris
Mealy Machines: Outputs depend on current state AND inputs
State Diagrams: Draw it before you code it!

Difficulty: Advanced Time estimate: 1 week Prerequisites: Project 11 (Traffic Light)

Real world outcome:

$ vvp vending_tb
Simulation:
  Insert 25¢ → Total: 25¢
  Insert 10¢ → Total: 35¢
  Insert 25¢ → Total: 60¢
  Press SODA (cost 50¢) → DISPENSING! Change: 10¢

  Insert 5¢ → Total: 5¢
  Insert 5¢ → Total: 10¢
  TIMEOUT (30 sec) → RETURNING 10¢

GTKWave shows state transitions and coin tracking!

Learning milestones:

Coin accumulation works → You understand stateful FSMs
Dispense and change work → You’ve done arithmetic in FSMs
Timeout works → You understand watchdog patterns

Project 13: Serial Pattern Detector (Finding 10110 in a bitstream)

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 3: Genuinely Clever
Business Potential: 3. The “Service & Support” Model (B2B Utility)
Difficulty: Level 3: Advanced (The Engineer)
Knowledge Area: Pattern Matching / State Machines
Software or Tool: Icarus Verilog, GTKWave
Main Book: “Language Implementation Patterns” by Terence Parr

What you’ll build: A circuit that watches a serial bitstream and asserts an output whenever it detects a specific pattern (like “10110”).

Why it teaches Verilog: This is a classic FSM problem that directly applies to packet detection in networking, barcode reading, and protocol framing. It’s also a common interview question!

Core challenges you’ll face:

Overlapping pattern detection (10110110 has two matches) → maps to FSM overlap handling
Moore vs Mealy implementation → maps to architecture trade-offs
Parameterizing the pattern → maps to reusable design

Key Concepts:

Sequence Detection FSM: ASIC World - FSM Sequence Detector
Overlapping Detection: Handle partial matches that could become new matches
Mealy Machine Advantage: Earlier detection (output depends on input+state)

Difficulty: Advanced Time estimate: 1 weekend Prerequisites: Project 11 (Traffic Light)

Real world outcome:

$ vvp pattern_tb
Bitstream: 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 0
Detected:  - - - - - ✓ - - ✓ - - - - - - ✓

Pattern "10110" found at positions 5, 8, and 15!
Overlapping detection works!

Learning milestones:

Simple pattern detected → You understand sequence FSMs
Overlapping patterns handled → You’ve mastered FSM edge cases
Parameterized pattern works → You can build reusable detectors

Level 4: Memory & Communication Interfaces

These projects interact with the outside world using standard protocols.

Project 14: Simple RAM (8 words × 8 bits)

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 3: Genuinely Clever
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 2: Intermediate (The Developer)
Knowledge Area: Memory Design / Storage
Software or Tool: Icarus Verilog, GTKWave
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A small RAM module with address, data_in, data_out, write_enable, and clock inputs. Then experiment with ROM (read-only memory).

Why it teaches Verilog: Memory is everywhere – caches, registers files, buffers. You’ll understand read/write timing, synchronous vs asynchronous reads, and how arrays work in Verilog.

Core challenges you’ll face:

Declaring memory arrays (reg [7:0] mem [0:7]) → maps to Verilog arrays
Synchronous write, synchronous vs async read → maps to timing trade-offs
Read-during-write behavior → maps to real FPGA memory behavior

Key Concepts:

RAM Design: “Digital Design and Computer Architecture” Chapter 5.5 - Harris & Harris
Memory Arrays: ChipVerify - Memory Modeling
Block RAM vs Distributed RAM: FPGA-specific optimization

Difficulty: Intermediate Time estimate: 3-4 hours Prerequisites: Project 6 (Flip-Flop)

Real world outcome:

$ vvp ram_tb
Write: addr=3, data=0xAB
Write: addr=5, data=0xCD
Read:  addr=3 → data=0xAB ✓
Read:  addr=5 → data=0xCD ✓
Read:  addr=0 → data=0x00 (never written) ✓

You've built memory! The foundation of all computing.

Learning milestones:

Write/read works → You understand memory operation
Async read vs sync read implemented → You understand timing trade-offs
ROM with initial values works → You can store constants

Project 15: UART Transmitter

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 4: Hardcore Tech Flex
Business Potential: 3. The “Service & Support” Model (B2B Utility)
Difficulty: Level 3: Advanced (The Engineer)
Knowledge Area: Serial Communication / Protocols
Software or Tool: TinyFPGA BX, USB-to-Serial adapter, terminal program
Main Book: “Making Embedded Systems” by Elecia White

What you’ll build: A UART transmitter that sends 8-bit bytes serially at a configurable baud rate (9600, 115200, etc.).

Why it teaches Verilog: UART is your first real communication protocol. You’ll implement a baud rate generator, shift register, and state machine that work together. You’ll talk to a real computer!

Core challenges you’ll face:

Baud rate generation from FPGA clock → maps to clock dividers
Serializing parallel data → maps to shift registers
Start bit, data bits, stop bit timing → maps to protocol implementation
Handling back-to-back bytes → maps to state machine design

Resources for key challenges:

UART Protocol Explained - Hasitha Algewatta
ben-marshall/uart - Simple reference implementation
TimRudy/uart-verilog - Well-documented with timing diagrams

Key Concepts:

UART Protocol: “Making Embedded Systems” Chapter 10 - Elecia White
Baud Rate Generation: Clock cycles per bit = FPGA_CLK / BAUD_RATE
Shift Register FSM: ASIC World - UART Model

Difficulty: Advanced Time estimate: 1 week Prerequisites: Project 8 (Shift Register), Project 11 (Traffic Light)

Real world outcome:

On your computer's terminal (screen /dev/ttyUSB0 115200):
  FPGA sends: Hello from FPGA!

You're sending real data to a real computer from hardware you built!

Learning milestones:

Correct waveform in GTKWave → You understand the protocol
Single character received correctly → Basic TX works
Continuous string transmission → You’ve built a real serial port!

Project 16: UART Receiver

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 4: Hardcore Tech Flex
Business Potential: 3. The “Service & Support” Model (B2B Utility)
Difficulty: Level 3: Advanced (The Engineer)
Knowledge Area: Serial Communication / Protocols
Software or Tool: TinyFPGA BX, USB-to-Serial adapter
Main Book: “Making Embedded Systems” by Elecia White

What you’ll build: A UART receiver that samples incoming serial data and reconstructs bytes.

Why it teaches Verilog: Reception is harder than transmission – you must detect the start bit, sample at the center of each bit, and handle timing variations. This teaches robust protocol implementation.

Core challenges you’ll face:

Start bit edge detection → maps to asynchronous signal handling
Sampling at bit center (oversample at 16x) → maps to clock domain crossing
Reconstructing bytes from bits → maps to deserialization
Signaling data ready → maps to handshaking

Key Concepts:

Oversampling: Sample at 16x baud rate to find bit center
Clock Domain Crossing: Input signal is asynchronous to FPGA clock
Synchronizer: Two flip-flops to prevent metastability

Difficulty: Advanced Time estimate: 1 week Prerequisites: Project 15 (UART TX)

Real world outcome:

Type on your computer terminal:
  You type: A
  FPGA receives: 0x41
  LEDs display: 01000001

Type: Hello
  FPGA echoes back: Hello (loopback test!)

Your FPGA can receive data from a computer!

Learning milestones:

Start bit detected → You understand edge detection
Single character received → Basic RX works
Echo test passes → You have bidirectional communication!

Project 17: SPI Master

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 4: Hardcore Tech Flex
Business Potential: 3. The “Service & Support” Model (B2B Utility)
Difficulty: Level 3: Advanced (The Engineer)
Knowledge Area: Serial Communication / Bus Protocols
Software or Tool: TinyFPGA BX with SPI peripheral (e.g., SPI Flash, ADC, display)
Main Book: “Making Embedded Systems” by Elecia White

What you’ll build: An SPI master that can communicate with external SPI peripherals (flash memory, sensors, displays).

Why it teaches Verilog: SPI is simpler than UART but adds clock and chip select signals. You control the clock, so timing is more deterministic. Many peripherals use SPI!

Core challenges you’ll face:

Generating SCLK from FPGA clock → maps to clock generation
MOSI/MISO shift registers → maps to bidirectional shift registers
Chip select timing → maps to control signal sequencing
Different SPI modes (CPOL, CPHA) → maps to protocol variations

Key Concepts:

SPI Protocol: “Making Embedded Systems” Chapter 10 - Elecia White
SPI Modes: Clock polarity and phase (0,0), (0,1), (1,0), (1,1)
Full Duplex: MOSI and MISO shift simultaneously

Difficulty: Advanced Time estimate: 1 week Prerequisites: Project 8 (Shift Register)

Real world outcome:

With SPI Flash chip:
  Read ID: Manufacturer=0xEF, Device=0x4016 (Winbond W25Q64)
  Read Page 0: FF FF FF FF FF FF FF FF (blank flash)
  Write "Hello" to address 0x100
  Read address 0x100: 48 65 6C 6C 6F (Hello!)

You're talking to external hardware!

Learning milestones:

SPI clock generated correctly → You understand master timing
Read device ID works → Basic communication works
Read/write flash works → Full SPI master implemented

Level 5: Complex System Projects

Putting it all together to build impressive, visual systems.

Project 18: VGA Pattern Generator

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 5: Pure Magic (Super Cool)
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 3: Advanced (The Engineer)
Knowledge Area: Video Output / Timing Generation
Software or Tool: FPGA with VGA port (iCEBreaker with VGA PMOD, or ULX3S)
Main Book: “Computer Graphics from Scratch” by Gabriel Gambetta

What you’ll build: A VGA controller that generates timing signals and outputs colored patterns (stripes, checkerboard, gradients) to a monitor.

Why it teaches Verilog: VGA requires precise timing – horizontal sync, vertical sync, blanking intervals. You’ll create a complex timing generator and see your digital logic displayed on a real monitor!

Core challenges you’ll face:

Generating 640x480 @ 60Hz timing (25.175MHz pixel clock) → maps to precise timing
Horizontal/vertical counters and sync pulses → maps to state-based timing
Color generation based on coordinates → maps to pattern synthesis
Front porch, back porch, sync widths → maps to protocol adherence

Resources for key challenges:

TinyVGA.com Timing Calculator - VGA timing reference
“Computer Graphics from Scratch” Chapter 1 - Rasterization basics

Key Concepts:

VGA Timing: Specific timing for sync pulses and blanking periods
Pixel Clock: 25.175 MHz for 640x480 @ 60Hz
Active vs Blanking: Only output color during active video

Difficulty: Advanced Time estimate: 1-2 weeks Prerequisites: Project 7 (Counter), Project 11 (FSM)

Real world outcome:

On a real VGA monitor connected to your FPGA:
  - Color bars test pattern (like old TV test signals)
  - Moving gradient that scrolls across screen
  - Bouncing ball animation
  - Your own pixel art!

You're generating real video output from hardware you designed!

Learning milestones:

Stable sync (monitor doesn’t flicker) → You got timing right
Static pattern displays → Color output works
Animation works → You’ve built a real graphics system

Project 19: Calculator with 7-Segment Display

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 4: Hardcore Tech Flex
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 3: Advanced (The Engineer)
Knowledge Area: System Integration / User Interface
Software or Tool: FPGA with buttons and 7-segment displays
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A calculator that takes button input for digits and operations, performs arithmetic, and displays results on 7-segment displays.

Why it teaches Verilog: This integrates everything: debouncers, FSM for input handling, ALU for computation, and display driving. It’s a complete embedded system in hardware!

Core challenges you’ll face:

Input FSM (digit entry, operation, equals) → maps to UI state machine
Multi-digit entry and display → maps to BCD and multiplexing
Display multiplexing (4 digits, 1 display controller) → maps to time-division multiplexing
Overflow and error handling → maps to edge case handling

Key Concepts:

Display Multiplexing: Scan through displays faster than eye can see
BCD (Binary Coded Decimal): Each digit stored separately
Input FSM: Num1 → Op → Num2 → = → Result

Difficulty: Advanced Time estimate: 2 weeks Prerequisites: Projects 3, 5, 9, 11

Real world outcome:

Physical calculator on your desk:
  Press: 1 2 + 3 4 =
  Display shows: 46

  Press: 9 9 × 9 9 =
  Display shows: 9801

You built a real calculator from scratch!

Learning milestones:

Digit entry works → Input FSM functional
Single operations work → ALU integrated
Multi-digit with display → Complete system working

Project 20: Pong Game on VGA

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 5: Pure Magic (Super Cool)
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 4: Expert (The Systems Architect)
Knowledge Area: Game Logic / Real-time Systems
Software or Tool: FPGA with VGA and buttons (iCEBreaker, ULX3S)
Main Book: “Computer Graphics from Scratch” by Gabriel Gambetta

What you’ll build: The classic Pong game running entirely in hardware – no CPU, no software, pure digital logic.

Why it teaches Verilog: This is a complete real-time interactive system: VGA output, game state machine, collision detection, player input, and scoring. All running in parallel as pure hardware!

Core challenges you’ll face:

Ball physics (position, velocity, bouncing) → maps to arithmetic at clock rate
Paddle control with buttons → maps to input integration
Collision detection → maps to comparators and game logic
Score display → maps to state integration
60 FPS real-time operation → maps to timing constraints

Key Concepts:

Game Loop in Hardware: Update state once per frame
Collision Detection: Compare ball position with paddle/wall boundaries
Synchronous Game State: All updates happen at frame rate

Difficulty: Expert Time estimate: 2-3 weeks Prerequisites: Project 18 (VGA), Project 9 (Debouncer)

Real world outcome:

On VGA monitor with buttons:
  - White ball bounces around screen
  - Two paddles controlled by buttons
  - Ball bounces off paddles
  - Score displayed at top
  - Classic 8-bit sound effects (optional)

You made a playable video game in HARDWARE!

Learning milestones:

Ball moves and bounces → Basic physics
Paddles respond to input → Input integration
Collisions work → Game is playable
Score tracking → Complete game!

FINAL PROJECT: Simple 8-bit CPU

The ultimate Verilog project – building your own CPU from scratch.

Final Project: 8-bit RISC CPU

File: VERILOG_FROM_ZERO_PROJECTS.md
Main Programming Language: Verilog
Alternative Programming Languages: VHDL, SystemVerilog
Coolness Level: Level 5: Pure Magic (Super Cool)
Business Potential: 1. The “Resume Gold” (Educational/Personal Brand)
Difficulty: Level 5: Master (The First-Principles Wizard)
Knowledge Area: Computer Architecture / CPU Design
Software or Tool: Icarus Verilog, FPGA for hardware implementation
Main Book: “Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris

What you’ll build: A complete 8-bit CPU with:

8 general-purpose registers
ALU (add, sub, and, or, shift)
Program counter
Instruction memory (ROM)
Data memory (RAM)
Control unit with instruction decoder
Simple assembly language

Why it teaches Verilog: This is the pinnacle of digital design. Every concept you’ve learned comes together: combinational logic (ALU), sequential logic (registers), FSMs (control unit), memory, and I/O.

Core challenges you’ll face:

Designing an instruction set → maps to architecture design
Fetch-Decode-Execute pipeline → maps to control FSM
ALU integration → maps to datapath design
Memory-mapped I/O → maps to interface design
Writing an assembler (in Python) → maps to tooling

Key Concepts:

CPU Architecture: “Digital Design and Computer Architecture” Chapters 6-7 - Harris & Harris
RISC Principles: Simple, fixed-length instructions
Datapath vs Control: Separation of concerns
Von Neumann Architecture: Single memory for code and data
Pipeline Basics: How CPUs achieve high throughput

Difficulty: Master Time estimate: 1-2 months Prerequisites: All previous projects (especially 5, 14, 18)

Real world outcome:

Your CPU running "blink.asm":
  ; Blink LED forever
  loop:
    LOAD R0, #0xFF    ; LED on
    OUT R0            ; Output to LED port
    CALL delay
    LOAD R0, #0x00    ; LED off
    OUT R0
    CALL delay
    JMP loop

LED blinks on your FPGA, controlled by YOUR OWN CPU!

You wrote an assembler, assembled a program, loaded it into memory,
and your CPU executed it. You built a computer.

Learning milestones:

Fetch works (PC increments, instruction read) → Instruction fetch unit complete
Arithmetic instructions work → Datapath functional
Jumps and branches work → Control flow implemented
Full programs run → You built a computer!

Project Comparison Table

Project	Difficulty	Time	Depth of Understanding	Fun Factor
1. Gate Library	Beginner	2-3 hrs	⭐⭐	⭐⭐
2. 4-to-1 MUX	Beginner	2-3 hrs	⭐⭐⭐	⭐⭐
3. 7-Segment Decoder	Beginner	3-4 hrs	⭐⭐⭐	⭐⭐⭐
4. Ripple Carry Adder	Beginner-Int	4-5 hrs	⭐⭐⭐⭐	⭐⭐⭐
5. 8-bit ALU	Intermediate	1 week	⭐⭐⭐⭐⭐	⭐⭐⭐⭐
6. D Flip-Flop	Beginner	2-3 hrs	⭐⭐⭐⭐	⭐⭐
7. Counter	Intermediate	4-5 hrs	⭐⭐⭐⭐	⭐⭐⭐⭐
8. LED Chaser	Intermediate	Weekend	⭐⭐⭐	⭐⭐⭐⭐⭐
9. Debouncer	Intermediate	4-5 hrs	⭐⭐⭐⭐	⭐⭐⭐
10. PWM Generator	Intermediate	4-5 hrs	⭐⭐⭐	⭐⭐⭐⭐
11. Traffic Light	Intermediate	Weekend	⭐⭐⭐⭐⭐	⭐⭐⭐⭐
12. Vending Machine	Advanced	1 week	⭐⭐⭐⭐⭐	⭐⭐⭐
13. Pattern Detector	Advanced	Weekend	⭐⭐⭐⭐	⭐⭐⭐
14. Simple RAM	Intermediate	3-4 hrs	⭐⭐⭐⭐	⭐⭐⭐
15. UART TX	Advanced	1 week	⭐⭐⭐⭐⭐	⭐⭐⭐⭐⭐
16. UART RX	Advanced	1 week	⭐⭐⭐⭐⭐	⭐⭐⭐⭐⭐
17. SPI Master	Advanced	1 week	⭐⭐⭐⭐	⭐⭐⭐⭐
18. VGA Patterns	Advanced	1-2 weeks	⭐⭐⭐⭐⭐	⭐⭐⭐⭐⭐
19. Calculator	Advanced	2 weeks	⭐⭐⭐⭐⭐	⭐⭐⭐⭐
20. Pong Game	Expert	2-3 weeks	⭐⭐⭐⭐⭐	⭐⭐⭐⭐⭐
Final: CPU	Master	1-2 months	⭐⭐⭐⭐⭐	⭐⭐⭐⭐⭐

Recommendation: Your Learning Path

If you have zero Verilog experience (start here):

Week 1-2: Foundations

Project 1: Gate Library (learn syntax, testbenches, simulation)
Project 2: 4-to-1 MUX (learn behavioral Verilog)
Project 3: 7-Segment Decoder (satisfying visual output)

Week 3-4: Sequential Logic

Project 6: D Flip-Flop (understand clocked logic)
Project 7: Counter (your first stateful design)
Get hardware! TinyFPGA BX or iCEBreaker

Week 5-6: Real Hardware

Project 8: LED Chaser (see it work on real LEDs!)
Project 9: Debouncer (essential for buttons)
Project 11: Traffic Light (your first real FSM)

Week 7-8: Communication

Project 15: UART TX (talk to your computer!)
Project 16: UART RX (bidirectional communication)

Week 9+: Choose Your Adventure

Graphics path: Project 18 (VGA) → Project 20 (Pong)
Computer architecture path: Project 5 (ALU) → Final CPU Project
Embedded systems path: Project 17 (SPI) → Real sensor projects

Tools & Resources Summary

Essential Tools (Free)

Icarus Verilog: Simulator - brew install icarus-verilog or apt install iverilog
GTKWave: Waveform viewer - brew install gtkwave or apt install gtkwave

Recommended Hardware

TinyFPGA BX (~$38): Beginner-friendly, USB programmable
iCEBreaker (~$70): More I/O, includes PMODs for VGA/audio
ULX3S (~$100): Powerful, built-in VGA, USB, WiFi

Key Books

“Digital Design and Computer Architecture, RISC-V Edition” by Harris & Harris - THE book for learning digital design
“Making Embedded Systems” by Elecia White - Real-world hardware interfacing
“Computer Systems: A Programmer’s Perspective” by Bryant & O’Hallaron - Deep computer understanding
“Code: The Hidden Language” by Charles Petzold - Conceptual foundations

Online Resources

Nandland - Excellent beginner tutorials
FPGA Tutorial - Comprehensive Verilog course
ChipVerify - Reference and examples
ASIC World - Classic tutorials
Project IceStorm - Open source FPGA toolchain

YouTube Channels

Ben Eater - Building computers from scratch
Robert Baruch - FPGA projects and tutorials
Phil’s Lab - FPGA and embedded projects

Remember: Verilog is about describing hardware that exists simultaneously, not writing sequential instructions. Every project builds this intuition. Start with Project 1, and within a few weeks, you’ll be building real hardware!