Project 12: PIO‑Based I2C/SPI Analyzer

Build a protocol‑aware analyzer that decodes I2C and SPI transactions in real time.

Quick Reference

Attribute Value
Difficulty Level 3: Advanced
Time Estimate 1-2 weeks
Main Programming Language C + PIO
Alternative Programming Languages Rust
Coolness Level Level 4: “bus detective”
Business Potential 3. Debugging tool
Prerequisites I2C/SPI basics, PIO sampling
Key Topics Edge detection, protocol decoding, timestamps

1. Learning Objectives

  1. Capture I2C/SPI edges without disturbing the bus.
  2. Decode addresses, data bytes, and ACK/NAK.
  3. Timestamp events with microsecond resolution.
  4. Handle multiple SPI modes.

2. All Theory Needed (Per-Concept Breakdown)

2.1 I2C Protocol Timing and Framing

Fundamentals

I2C is a two‑wire bus with start/stop conditions, 7/10‑bit addresses, and ACK/NAK bits.

Deep Dive into the concept

I2C defines START as SDA falling while SCL is high, STOP as SDA rising while SCL high. Bits are sampled on SCL rising edges. Clock stretching means the slave can hold SCL low. A decoder must detect START/STOP, then sample SDA on each SCL rising edge to reconstruct bytes. Timing violations or missing ACKs should be reported.

2.2 SPI Modes and Sampling

Fundamentals

SPI uses separate lines for clock and data; CPOL/CPHA define sampling edges.

Deep Dive into the concept

There are four SPI modes. A decoder must sample MOSI/MISO on the correct edge and align bytes by chip‑select. If CPHA is wrong, bits appear shifted. The analyzer should allow selecting mode or auto‑detecting it.

2.3 Timestamping and Event Logs

Fundamentals

Analyzers are useful when you can correlate events with time. Use a timer or cycle counter to timestamp edges.

Deep Dive into the concept

Timestamp each START/STOP, byte, and ACK/NAK. Use a high‑resolution timer or DMA timestamps to preserve ordering. A compact log format reduces bandwidth.

3. Project Specification

3.1 What You Will Build

A passive I2C/SPI analyzer that reports decoded transactions over UART/USB and flags timing errors.

3.2 Functional Requirements

  1. Detect I2C START/STOP and decode bytes.
  2. Decode SPI for at least two modes.
  3. Timestamp events with µs resolution.
  4. High‑impedance input to avoid bus loading.

3.7 Real World Outcome

Capturing a known I2C sensor read shows correct address, register, data, and ACK sequence.

4. Solution Architecture

PIO edge capture -> DMA buffer -> Decoder -> Host log

5. Implementation Guide

5.10 Implementation Phases

  • Phase 1: Raw edge capture
  • Phase 2: I2C decode
  • Phase 3: SPI decode + timestamps

6. Testing Strategy

  • Decode a known I2C transaction
  • Verify SPI modes with known pattern

7. Common Pitfalls & Debugging

  • Sampling on wrong edge
  • Missing START/STOP due to incorrect pin config

8. Extensions & Challenges

  • Add bus speed measurement
  • Add automatic SPI mode detection

9. Submission / Completion Criteria

Minimum Viable Completion:

  • I2C decoding with correct ACK/NAK.

Full Completion:

  • SPI decoding for at least two modes.

Excellence:

  • Timestamped event log with error detection.