Learn Chisel & RISC-V: From Zero to Hardware Architect

Goal: Deeply understand Hardware Construction Languages (HCLs) by mastering Chisel. You will move beyond writing static “netlists” in Verilog to building programmable hardware generators. By the end, you’ll be able to design, simulate, and implement custom RISC-V processor extensions, leveraging Scala’s object-oriented and functional power to create reusable, parameterizable silicon.

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Why Chisel & HCLs Matter

In the 1980s, Verilog and VHDL revolutionized hardware design by moving from schematic entry to text-based Hardware Description Languages (HDLs). However, modern chips have billions of transistors, and HDLs have become the “assembly language” of hardware—verbose, error-prone, and difficult to scale.

Chisel (Constructing Hardware in a Scala Embedded Language) represents the next leap: Hardware Construction Languages (HCLs). Instead of describing what the hardware is, you write a Scala program that generates the hardware.

The Paradigm Shift: From Description to Construction

Feature	Traditional HDL (Verilog/VHDL)	Modern HCL (Chisel)
Abstraction	Static Netlists / Low-level RTL	High-level Generators / Meta-programming
Reuse	Copy-paste or complex generate blocks	Scala Libraries, OOP, Functional Patterns
Verification	Separate Testbench Languages (SystemVerilog)	Unified Scala-based testing (ChiselTest/PeekPoke)
Verification	Proprietary Tools often required	Open-source ecosystem (FIRRTL, Treadle, Verilator)

The Chisel Compilation Flow

  Your Scala Code (*.scala)
          │
          ▼
    ┌─────────────┐
    │ Chisel Lib  │ (Hardware Construction)
    └─────────────┘
          │ (Execution of Scala Program)
          ▼
   ┌───────────────┐
   │    FIRRTL     │ (Intermediate Representation)
   └───────────────┘
          │ (Transformations & Optimizations)
          ▼
   ┌───────────────┐
   │ Verilog/C++   │ (For Synthesis or Simulation)
   └───────────────┘

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Core Concept Analysis

1. Hardware Generators: The “Killer App”

In Chisel, you don’t just build a 32-bit Adder. You build an Adder(width: Int) generator. Scala’s type system ensures that if you pass width = -1, the compiler catches the error before you ever try to simulate it.

Scala Parameters (N bits, Flow control type, etc.)
        │
        ▼
┌──────────────────┐
│ Chisel Generator │───────► Hardware Instance A (8-bit)
└──────────────────┘───────► Hardware Instance B (64-bit)

2. Basic Building Blocks: Modules & Bundles

• Modules: The unit of hierarchy (like a Verilog module).
• Bundles: Groups of signals (like a C struct or SystemVerilog interface).
• IO: The port list of a module, wrapped in IO().

       ┌─────────────────────────┐
       │         Module          │
       │  ┌───┐           ┌───┐  │
IN ───►│IO │──► Logic ──►│IO │───► OUT
       │  └───┘           └───┘  │
       └─────────────────────────┘

3. Registers and State

Unlike Verilog, where reg is often confusingly used for combinational logic, in Chisel, a Reg is always a hardware register (D-Flip-Flop).

          ┌──────────┐
  D ─────►│ Register │─────► Q
          │          │
Clock ───►│ (Implicit)│
          └──────────┘

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